Synopsys Analog, Mixed Signal and Full Custom Design & Verification Flow
Вебинар компании SYNOPSYS об инструментах разработки интегральных схем на транзисторном уровне. Участие — бесплатно. Язык вебинара — Английский
Synopsys Analog, Mixed Signal and Full Custom Design & Verification Flow
AGENDA
- Custom Compiler Schematic Capture and Simulation Environment
- SPICE simulation
- Mixed signal Verification
- Custom Compiler Layout Environment
- Q&A
Presenters:
- Andrew Milne - Senior Staff AE, based in the Reading UK offic
- Damian Roberts - Senior Staff AE, based in the Reading UK office
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